Prior art DC-DC converters, known and widely used as inexpensive DC power sources of the simple structure, utilize a switching element turned on and off to intermittently supply DC voltage from DC power source to a transformer which then converts DC voltage into a high frequency power to supply stabilized DC power to an electric load through a rectifying smoother. A prior art DC-DC converter exemplified in FIG. 6 comprises a primary winding 2a of a transformer 2 and a MOS-FET 3 as a switching element connected in series to a DC power source 1; a main rectifying smoother 4 which comprises a main rectifying diode 5 and a main smoothing capacitor 6 connected to a secondary winding 2b of transformer 2; an auxiliary rectifying smoother 7 which comprises an auxiliary rectifying diode 8 and an auxiliary smoothing capacitor 9 connected to a drive winding 2c of transformer 2; an output voltage detector 10 for detecting DC output voltage VO from main rectifying smoother 4; a current detecting resistor 16 for discerning winding current ID flowing through the primary closed circuit of transformer 2 in the form of detection voltage VOCP; and a primary control circuit 12 for producing drive signals VG to turn MOS-FET 3 on and off in response to detection signals transmitted through a photo-coupler 11 from output voltage detector 10 and detection voltage VOCP from current detecting resistor 16. Primary and secondary windings 2a and 2b of transformer 2 are coupled with the adverse polarity from each other. DC-DC converter shown in FIG. 6 is operated to cause primary control circuit 12 to produce drive signals to MOS-FET 3 which thereby is turned on and off so that the converter produces DC output voltage VO to electric load from secondary winding 2b of transformer 2 through main rectifying smoother 4 and DC output terminals 13 and 14, while drive winding 2c of transformer 2 provides power source voltage VCC to primary control circuit 12 through auxiliary rectifying smoother 7.
Primary control circuit 12 comprises a normal power supply 17 for generating a reference voltage VE1; a resistor 18 which has one end connected to normal power supply 17 and the other end connected to a light receiver 16 of a photo-coupler 11; a comparator 19 for comparing detection voltage VOSP simultaneously applied on current detecting resistor 16 and non-inverted terminal+of comparator 19 with regulatory voltage VM simultaneously applied on a junction of resistor 18 and light receiver 11b of photo-coupler 11 and on inverted terminal −of comparator 19; an oscillator 20 for generating pulse signals of constant frequency; and a RS flip flop (RSFF) 21 which is set by a pulse signal at set terminal S from oscillator 20 and reset by an output signal at reset terminal R from comparator 19 for producing drive signals VG to a gate terminal of MOS-FET 3. Upon start-up of the converter, electric current flows from DC power source 1 through a trigger resistor 15 to auxiliary capacitor 9 to electrically charge capacitor 9 and then the converter commences the operation when capacitor 9 is charged to a given operating voltage level for primary control circuit 12 which is thereafter activated by drive power VCC supplied from drive winding 2c of transformer 2 through auxiliary rectifying smoother 7.
In triggering operation of prior art DC-DC converter shown in FIG. 6, a main switch not shown is turned on to send an electric current from DC power source 1 of DC voltage E through trigger resistor 15 to auxiliary capacitor 9 of auxiliary rectifying smoother 7 and electrically charge auxiliary capacitor 9. When charged voltage in capacitor 9 comes to operating voltage for primary control circuit 12, power source voltage VCC is applied on all elements 19 to 21 in primary control circuit 12 to cause primary control circuit 12 to start the operation. Once started, oscillator 20 produces pulse signals of a constant frequency to set terminal S of RSFF 21 which is then set to generate a drive signal VG of high voltage level from output terminal Q of RSFF 21 to gate terminal of MOS-FET 3 to turn MOS-FET 3 on.
When MOS-FET 3 is turned on, winding current ID flows from DC power source 1 through the primary closed circuit including primary winding 2a of transformer 2, MOS-FET 3 and current detecting resistor 16 to DC power source 1 to accumulate energy in transformer 2. Current detecting resistor 16 converts winding current ID therethrough into a detection voltage VOCP corresponding to winding current ID. Detection voltage VOCP on current detecting resistor 16 is also applied on non-inverted input terminal of comparator 19 which compares detection voltage VOCP with regulatory voltage VM at inverted input terminal−of comparator 19 connected to a junction of resistor 18 and light receiver 11b of photo-coupler 11. When detection voltage VOCP on current detection resistor 16 reaches regulatory voltage VM on junction of resistor 18 and light receiver 11b, comparator 19 delivers an output signal of high voltage level to reset terminal R of RSFF 21 to reset RSFF 21. Thus, RSFF 21 develops a drive signal VG of low voltage level from Q output terminal to gate terminal of MOS-FET 3 to turn MOS-FET 3 off.
When MOS-FET 3 is switched off, energy accumulated in transformer 2 is released from secondary winding 2b of transformer 2 by producing output current from secondary winding 2b through main rectifying diode 5 and main smoothing capacitor 6 of main rectifying smoother 4 to supply DC power to electric load from DC output terminals 13 and 14 under DC voltage VO. At the same time, energy stored in transformer 2 is also discharged from drive winding 2c of transformer 2 through auxiliary rectifying diode 8 and auxiliary smoothing capacitor 9 of auxiliary rectifying smoother 7 to apply power source voltage VCC on primary control circuit 12. DC output voltage VO between DC output terminals 13 and 14 is compared with a reference voltage not shown in output voltage detector 10 which produces an error signal, the potential difference between DC output voltage VO and reference voltage so that error signal is transformed into optical light output by light emitter 11a of photo-coupler 11 and transmitted to light receiver 11b. Accordingly, light receiver 11b allows electric current of the amount corresponding to magnitude of error signal to flow through light receiver 11b and thereby provide regulatory voltage VM on junction of resistor 18 and light receiver 11b of photo-coupler 11. Consequently, under the heavier load, DC output voltage VO becomes lower to cause a smaller amount of electric current to flow through light emitter and receiver 11a and 11b, elevate regulatory voltage VM, extend pulse width of drive signals VG from RSFF 21 to gate terminal of MOS-FET 3, and thereby widen the on-period of MOS-FET 3. Adversely under the lighter load, DC output voltage VO becomes higher to cause a larger amount of electric current to flow through light emitter and receiver 11a and 11b, diminish regulatory voltage VM, narrow pulse width of drive signals VG from RSFF 21 to gate terminal of MOS-FET 3, and thereby shorten the on-period of MOS-FET 3. Specifically, under the heavier load, output voltage detector 10 produces decreased error signal to boost regulatory voltage VM SO that comparator 19 produces reset signals at a late stage to RSFF 21 to extend the on-period of MOS-FET 3. To the contrary, under the lighter load, output voltage detector 10 produces increased error signal to lessen regulatory voltage VM so that comparator 19 produces reset signals at an early stage to RSFF 21 to shorten the on-period of MOS-FET 3. In this way, the on-period of MOS-FET 3 can appropriately be adjusted to control winding current ID passing through the primary closed circuit of transformer 2. The foregoing operation is repeated to moderate, to a desired voltage level, DC output voltage VO applied from DC output terminals 13 and 14 to load.
As understood from the circuit, heavy load causes winding current ID through MOS-FET 3 to increase, and current detecting resistor 16 picks out winding current ID through MOS-FET 3 as a detection voltage VOCP corresponding to winding current ID. In this case, when detection voltage VOCP reaches or exceeds reference voltage VE1 of normal power source 17, primary control circuit 12 comes to the overcurrent condition, and winding current ID can never increase any more. Under this excessive current condition, a maximum amount of winding current ID flows through MOS-FET 3. In this way, as a large amount of winding current ID passes through MOS-FET 3 under the overcurrent or heavy load condition, precipitous pulsatile surge voltages occur on primary, secondary and drive windings 2a, 2b and 2c of transformer 2.
In response to recent overwhelming requirement to reduced consumption power in DC-DC converters during the standby time, most of primary control circuits 12 involve generally very low power-consumptive CMOS (complementary metal oxide semiconductor) circuits of very high input impedance. When winding current ID becomes an overcurrent, it results in a surge voltage appearing on drive winding 2c of transformer 2 so that higher and steeply rising power source voltage VCC would be applied from drive winding 2c through auxiliary rectifying smoother 7 to primary control circuit 12, in particular, if primary control circuit 12 is assembled with CMOS circuits. In this case, however, there is a risk that power source voltage VCC may rise and exceed an withstand voltage of primary control circuit 12, and for that reason, prior art DC-DC converter exemplified in FIG. 6 comprises a Zener diode 22 connected in parallel to auxiliary rectifying smoother 7 for absorbing surge energy to prevent abnormal boost in power source voltage VCC. When a surge of extremely large energy occurs in power source voltage VCC, Zener diode 22 cannot sufficiently absorb such a surge and may bring primary control circuit 12 into breakdown. In another aspect, Zener diode 22 unfavorably clamps power source voltage VCC for primary control circuit 12 at the Zener or breakdown voltage, preventing exact detection of excessive voltage in the primary side of DC-DC converter.
To solve the foregoing problems, for example, Japanese Patent Disclosure No. 6-90561 published Mar. 29, 1994, shows a power source device which comprises an overvoltage protector connected to output terminals of a drive winding in a transformer to provide source power from drive winding to a control circuit. The overvoltage protector comprises a capacitor connected in parallel to drive winding, and a series circuit of a Zener diode and a resistor connected in parallel to drive winding to clamp emergent overvoltage below operation voltage for control circuit by the overvoltage protector. Also, Japanese Patent Disclosure No. 9-265328 published Oct. 7, 1997, exhibits an active dummy circuit which comprises an error amplifier connected to a secondary winding of a transformer to produce an error signal when output voltage from secondary winding exceeds a reference voltage, and a dummy loading circuit turned on by the error signal from error amplifier to pass a dummy current through dummy loading circuit for absorbing a part of overvoltage in transformer. If an operation continues to repress overvoltage for a long time in either of the circuits disclosed in these references, overvoltage protector and dummy loading circuit disadvantageously increase consumed electric power, giving rise to an associated excessive temperature rise which may cause damage to elements or circuits. Accordingly, alleviation of effect by such heating in circuits needs increased thermal capacity which disadvantageously requires a larger size or expensive converter.
An object of the present invention is to provide a DC-DC converter capable of detecting overvoltage resulted from surge voltage in a primary side to repress rapid rise in power source voltage for a control circuit. Another object of the present invention is to provide a DC-DC converter which can inhibit power loss during the protection against overvoltage.